Complementary insulated gate field effect transistor structure and process for fabricating the structure

ABSTRACT

A complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate and a process for fabricating the structure incorporate oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Q ss  in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.

This is a division of application Ser. No. 475,358 filed June 3, 1974,now abandoned.

This invention relates to complementary insulated gate field effecttransistor structures and processes for fabricating such structures, andmore particularly to an improved insulated gate field effect transistorstructure and a process for fabricating the structure which incorporateoxide isolation of active device regions such as the isoplanar oxideisolation as described in U.S. Pat. No. 3,648,125 issued to Peltzer,counterdoping of the p-well with impurities of opposite type to obtain acomposite doping profile, reduction of Q_(ss) in the isoplanar oxide,doping of the gate and field oxides with a chlorine species, andphosphorus doping of the polycrystalline silicon gates.

BACKGROUND OF THE INVENTION

Complementary field effect circuit arrangements employ an n-channel anda p-channel field effect transistor which are coupled so that the sourceor drain of one device is connected to the source or drain of the otherdevice. In any mode of circuit operation, one of the devices will befunctioning and the other will be off. When operating conditions withinthe circuit dictate that the functioning device turns off, the devicewhich was previously off will begin to function due to interconnectionof the sources and/or drains of the two devices. This concept was firstdisclosed by Wanlass in U.S. Pat. No. 3,356,858. It is especially usefulbecause no additional power is required to switch either of the devices.Switching is an inherent attribute of circuit operation.

Conventional complementary field effect devices are fabricated asconductor-insulator-semiconductor structures with interconnectionsbetween particular sources or drains of the n-channel and p-channeldevices. The conductors may be metal or conductive polycrystallinesilicon. Silicon dioxide is the most widely used insulator and singlecrystal silicon is the most widely used semiconductor substrate. Typicalcomplementary metal oxide semiconductor (CMOS) structures are fabricatedon an n-type substrate rather than on a p-type substrate because it iseasier to obtain desirable threshold voltages for both the n-channel andp-channel complementary devices. The p-well required for the n-channelcomplement is obtained by diffusing a lightly doped p-region into then-type substrate. In some devices all n-channel devices are fabricatedin a common p-well, and p-channel devices are fabricated in then-substrate so that much of the overall area is taken up withinterconnections between the n-channel and p-channel devices. Whereindividual p-wells are used for the n-channel devices, isolation of thep-channel field effect transistors is sometimes achieved by heavilydoped channel stops. These channel stops occupy a large amount of wafersurface area, degrade operating speed and limit the voltage range.Recently, polycrystalline silicon has been used in place of metal forthe gate electrodes of the devices, but although transient performanceis slightly improved, a negligible reduction in area has been effected.Also, the standard dopant, boron, which is placed in the polycrystallinesilicon to render it conductive and to obtain a low threshold, possessesthe property that it may diffuse through the gate oxide in the presenceof hydrogen and degrade the device. And, prior-art CMOS devices areknown to experience impurity migration through both the gate and fieldoxides with resultant impairment in the operating characteristics of thedevices. Finally, the presence of uncontrolled amounts of fixed surfacestates charges, due typically to non-stoichiometric composition of theSiO₂, also impairs the operating characteristics of the devices.

SUMMARY OF THE INVENTION

The invention described herein overcomes the known deficiencies ofconventional CMOS structures. Further, the structure exhibits many othersignificant advantages over conventional metal gate non-oxide-isolatedCMOS circuits. The disclosed structure has a broad operating range ofapproximately 3 to 15 volts, increased packing density, greater devicestability and better control of threshold values for the respectivedevices.

A complementary insulated gate field effect transistor structure hasn-channel and p-channel conductor-insulator-semiconductor devices formedin the same semiconductor substrate and includes a semiconductorsubstrate of a first conductivity type having a major surface, acomposite conductivity well in the substrate which occupies a portion ofthe major surface, the composite well containing impurities of a firstconductivity type and of a second conductivity type opposite to thefirst conductivity type to produce a net conductivity of said secondtype which is low near the major surface to provide a low threshold fora device within the well and high deep within the well to produce highbreakdown voltages across the well/substrate junction, a firstconductor-insulator-semiconductor field-effect device having a firsttype channel conductivity and having a pair of source/drain regions ofthe first conductivity type located in spaced-apart relation in thesurface of the composite conductivity well adjacent the major surface, afirst gate insulating material overlying the portion of the majorsurface occupied by the well and spanning the distance between the pairof source/drain regions of the first conductivity type, and a first gateelectrode overlying the first gate insulating material, a secondconductor-insulator-semiconductor field-effect device having a secondtype channel conductivity and having a pair of source/drain regions ofthe second conductivity type in spaced-apart relation adjacent the majorsurface of the semiconductor substrate, a second gate insulatingmaterial overlying the major surface of the semiconductor substrate andspanning the distance between the pair of source/drain regions of thesecond conductivity type, and a second gate electrode overlying thesecond gate insulating material, and isolation regions formed contiguouswith the semiconductor substrate and around the first and secondconductor-insulator-semiconductor devices.

The present invention further comprises a process for fabricating acomplementary insulated gate field-effect transistor structure havingn-channel and p-channel devices in the same semiconductor substrate,comprising the steps of forming isolation regions in selected portionsof a semiconductor substrate adjacent a major surface thereof, thesubstrate having a first conductivity type and the isolation regionssubstantially surrounding first and second active device regions, eachof the active device regions occupying portions of the major surface,forming a composite conductivity well in the first active device regionin the semiconductor substrate by introducing impurities of the firstconductivity type and of a second conductivity type opposite to thefirst conductivity type to produce a net conductivity concentration ofthe second conductivity type which is low near the major surface toprovide a low threshold for a device within the well and high deepwithin the well to produce high breakdown voltages across thewell/substrate junction, forming a conductor-insulator-semiconductorfield-effect device having a first channel conductivity type within thecomposite well in the first active device region, and forming aconductor-insulator-semiconductor field-effect device having a secondchannel conductivity type in the second active device region within thesubstrate.

The present invention further comprises a process for fabricating acomplementary insulated gate field-effect transistor structure whereinp-channel and n-channel devices are formed within the same semiconductorsubstrate, comprising the steps of applying a thermal oxidation maskingmaterial to a layer of n-type silicon, defining the thermal oxidationmaterial to establish protected active device regions and to open upisoplanar isolation regions, introducing a lightly doped n-type impurityin the substrate in the isoplanar isolation regions, heating thesemiconductor substrate in the presence of an oxidizing agent to formisolation islands of silicon dioxide, removing the thermal oxidationmasking material, predepositing n-type and p-type impurities in at leastone active device region, heating the substrate to drive the n-type andp-type impurities into the substrate to form a composite conductivitywell, the relative concentration of the n-type and p-type impuritiesproducing a low net p-type concentration near the surface of the welland a high net p-type concentration deep within the well, thermallygrowing a thin layer of silicon dioxide in the active device regions,depositing a conductive layer of polycrystalline silicon, defining thelayers of silicon dioxide and polycrystalline silicon to produceinsulated gate electrodes for the p-channel and n-channel devices,predepositing boron adjacent both sides of a defined gate electrode inan active device region formed in the layer of n-type silicon to formthe source/drain regions of a p-channel field-effect device,predepositing phosphorus adjacent both sides of a defined gate electrodein an active device region formed in the composite well to produce thesource/drain regions of an n-channel field-effect device, thermallydriving in the impurities predeposited in the source/drain regions ofthe p-channel and n-channel devices, forming a further layer ofelectrical insulation over the isolation islands and applying aconductive layer and defining said conductive layer to connect one ofthe source/drain regions of the p-channel field-effect device and one ofthe source/drain regions of the n-channel field-effect device and toeffect external electrical coupling with the remaining source/drainregions of the n-channel and p-channel field-effect devices.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the structure and process of thepresent invention, reference may be had to the drawings which areincorporated herein by reference and in which:

FIG. 1 illustrates an intermediate process step after selectiveformation of layers of silicon dioxide 12b and 12d on n-substrate 10,selective formation of layers of oxidation masking material 14b and 14d,and introduction of a field implant to regions 17a, 17c and 17e;

FIG. 2 is a further view of FIG. 1 after growth of isoplanar isolationoxide 20a, 20c and 20e, removal of oxidation masking material 14b, and14d and layers of silicon dioxide 12b and 12d, and application ofphotoresist layer 21 and introduction of p-well double ion implant 23d;

FIG. 3 is a further view of FIG. 2 after thermal drive-in of the p-wellimplant to form p-well 23d and of the field implant to form expandedfield implant regions 17a, 17c and 17e, growth of the gate oxide layers30b and 30d, and deposition of polycrystalline silicon layer 31;

FIG. 4 is a further view of FIG. 3 after definition of thepolycrystalline silicon gates 34 and 35, definition of the gate oxide33, and implantation of p⁺ impurities in source/drain regions 36;

FIG. 5 is a further view of FIG. 4 after application of a thinphotoresist layer 40, definition of gate oxide 39 and implantation of n⁺impurities in source/drain regions 37;

FIG. 6 is a further view of FIG. 5 after thermal drive-in of thep^(+-source/drain) regions 36 and the n^(+-source/drain) regions 37,application of thick oxide layer 46 and definition of polycrystallinesilicon gate insulation 43 and 44;

FIG. 7 is a further view of FIG. 6 after conductive connectors have beenapplied and defined to interconnect one p^(+-source/drain) region of thep-channel device and one n^(+-source/drain) region of the n-channeldevice and to provide external electrical communication with theremaining source/drain regions; and

FIG. 8 is a graph illustrating the composite impurity concentration inthe p-well as a result of the counterdoping procedure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, the substrate 10 is shown, in this preferredembodiment, to be n-conductivity-type silicon. With ann-conductivity-type substrate and associated p-well, the thresholdvoltages of the two complementary devices are matched more closely thanis possible for devices in a p-conductivity-type substrate andassociated n-well, if the compensating effect of p-well implantation isconsidered. Complementary devices formed in a p-type substrate with anassociated n-well could have matched threshold voltages provided anadditional impurity was introduced underneath the gate of the p-channeldevice. With this proviso, the disclosure herein of complementaryfield-effect devices formed in an n-substrate and associated p-well alsopertains to complementary field-effect devices formed in a p-substrateand associated n-well with the appropriate substitution of analogousprocess steps.

A layer of oxidation masking material 14 is applied to the surface ofsubstrate 10. This material serves to mask the active device regionswhile isolation regions are grown. It has been found advantageous tointerpose a layer of silicon dioxide 12 between oxidation maskingmaterial 14 and the silicon substrate 10 in order to prevent thecreation of defects in the substrate upon cooling and to provide a moredesirable geometry to the isoplanar oxide islands. The inclusion of asilicon dioxide layer 12 appears to reduce structural stressesexperienced by the substrate upon cooling. For example, if the oxidationmasking material 14 is silicon nitride, Si₃ N₄, the silicon dioxidelayer 12 will be in a state of compression while the silicon nitride 14will be in a state of tension with respect to the silicon substrate dueto the differences in coefficient of thermal expansion. Thecountervailing forces may protect the substrate. As shown, both thesilicon dioxide and the silicon nitride are defined by carrying out aphotoresist masking sequence to protect active device regions 15b and15d and to expose isolation regions 15a, 15c and 15e.

As used above and throughout this specification, the phrase "photoresistmasking sequence" refers to the well-known sequence of applying auniform layer of a photoresist polymer, selectively exposing thephotoresist by radiation of appropriate wavelength, developing thephotoresist to leave a desired pattern, performing an active step suchas diffusion or forming metal contacts, and removing the photoresistpolymer. A complete photoresist masking sequence is also called amasking step. The details of each individual dual masking step are notshown in the drawings and should be inferred from the use of the term"masking step."

An n-type field implant, typically arsenic, is then introduced intoisolation regions 15a, 15c and 15e. Preferably the field implant isintroduced by ion implantation because the dosage and energy ofimplantation can be carefully controlled. In one embodiment a fieldimplantation energy of 40KeV is employed. The field implant may also beintroduced by diffusion. In either case, the impurity atoms enter thesurface of the substrate and repose at a shallow depth. This step iscalled predeposition. The silicon nitride overlying the silicon dioxidein the active device regions 15b and 15d masks the substrate regions andprevents any of the field implant impurity from reaching substrate 10.When driven into the substrate, such a field implant slightly raises thesurface concentration of n-type impurities in the n-substrate 10 andprevents inversion of the substrate underneath the isolation regions.Such inversion would occur between p-type source/drain regions of thep-channel device and the p-well, i.e., between source/drain region 36dand p-well 23d of FIG. 4. In effect, the implant forms a channel stopbut requires much less surface area. The concentration of the fieldimplant is typically about one order of magnitude lower than either thesubstrate or p-well concentrations so that even though the n-typeimplant reduces the p-conductivity-type concentration and enhances thelikelihood of inversion of the p-well between the n-type source/drainregions of the n-channel device and the n-substrate 10, the p-well isrelatively so heavily doped beneath shallow well depths that the netp-type concentration under the isolation islands remains high enough toprevent inversion of the p-well for voltages up to about 25 volts.

Referring now to FIG. 2, isolation islands 20 are formed in isolationregions 15a, 15c and 15e. Several versions of oxide isolation have beendeveloped commercially. Generally, they include surrounding activedevice regions with thick layers of silicon dioxide, also called fieldoxide. The isoplanar process as set forth in U.S. Pat. No. 3,648,125 isone such process. In the isoplanar process, silicon dioxide is grownfrom the silicon substrate by application of an oxidizing agent such asoxygen or water vapor at a temperature in the range of 900°-1250° C. Inone embodiment, a 1.8μ layer of isolation oxide is grown by subjectingthe substrate to a temperature of 1000° C. in a wet oxygen ambient for16 hours. The general thermal oxidation kinetics of this silicon dioxidegrowth have been reported previously. See B. E. Deal and A. S. Grove,"General Relationship for the Thermal Oxidation of Silicon." Journal ofApplied Physics, V.36, No. 12, pp. 3770-3778 (1965). The silicon dioxidegrows into and rises above the surface of the substrate to formisolation islands 20a, 20c and 20e which surround (in athree-dimensional structure) active device regions 15b and 15d. Thepredeposited field implant moves into the substrate ahead of theexpanding mass of silicon dioxide and, due to the elevated temperature,is dispersed even further into the substrate as shown by region 17c ofFIG. 3. Oxidation masking material 14 serves to prevent oxidation in theactive device regions 15b and 15d. After formation of isolation islands20, the masking material 14 along with the underlying silicon dioxide 12is stripped by well-known etching techniques.

Next, a masking step as evidenced by a layer of photoresist 21 isperformed to permit the predeposition of impurities in the p-wellregion. Both p-type and n-type impurities are introduced to thesubstrate and then thermally driven in. This counterdoping procedureproduces a highly desirable doping profile. The concentration of thep-type impurities in the profile achieved is great enough deep withinthe well so that inversion of the p-well between the n-type substrateand the n-type source/drain regions of the n-channel device will notoccur until very high voltages, on the order of 25 volts, are reached,even after the n-type field implant is considered. And, theconcentration of the p-type impurities in the profile is low enoughbetween the two n-type source/drain regions so that the n-channel devicewill operate at a suitably low threshold voltage on the order of 1.5volts. These two features of the doping profile are shown by thecomposite profile (dotted line) of FIG. 8. They are achieved bycounterdoping a p-type impurity with an n-type impurity in active deviceregion 15d. In effect, the n-type impurity is doped of the p-typeimpurity to lower the p-type concentration near the surface. As shown inFIG.. 8, the p-type impurity, boron, is introduced and thermally drivenin. Then, a lesser amount of an n-type impurity, arsenic, is introducedand thermally driven in. Ion implantation is the preferred method ofintroduction because the dosage rate and energy of implantation can becarefully controlled. The thermal drive-in step theoretically could beomitted if a suitably high energy of implantation is achieved, but as amatter of practicality will usually be used. In this embodiment theboron is implanted at an energy of 80 KeV and reaches a predepositiondepth of about 0.3-0.4μ while the arsenic is implanted at an energy of170 KeV and reaches a predeposition depth of about 0.1μ. When thermallydriven in, the boron reaches a depth of about 10μ and the arsenicreaches a depth of about 4μ and counterdopes the boron to produce thedesired composite concentration profile. In an alternative embodiment,the arsenic and boron are introduced simultaneously and thermally drivenin together. In the subsequent drive-in diffusion, advantage is taken ofthe approximate 2 : 1 ratio in diffusivity of boron to arsenic to obtainessentially a p-type profile deep within the well and a low p-typeconcentration near the surface. Other n-type and p-type impurities maybe used in the same manner so long as the composite doping profiledescribed herein is obtained. Prior attempts to obtain such a compositeprofile have involved contrived and complicated techniques whichgenerally have been unsatisfactory. The process of the present inventionachieves the desired composite profile in a reliable and reproduciblemanner.

The drive-in of the two impurities in the p-well is shown to becompleted in FIG. 3. This drive-in diffusion is accomplished afterstripping the photoresist 21. The drive-in is typically accomplished athigh temperatures on the order of 1200° C. in inert atmospheres such asnitrogen. In one aspect of the process of the present invention, a smallamount of oxygen is introduced to the inert atmosphere to prevent theaccumulation of positive charge Q_(ss) in the isolation oxide 20. Thepositive charge Q_(ss) in the silicon dioxide near the silicon/silicondioxide interface has been found to be caused by the generation ofdeficiency sites or ionized silicon species in the silicon dioxideduring the high-temperature anneal of the drive-in diffusion of thedouble ion implant. The high-temperature anneal produces deficiencysites in the silicon dioxide, e.g., sites at which SiO⁺ radicals areformed by driving out oxygen atoms. The presence of these positivecharges in high enough concentration can lead to inversion of thep-well, causing leakage between the two n^(+-source/drain) regions orbetween the n^(+-source/drain) regions and the n-substrate. It has beenfound that an atmosphere of about 98 percent N₂ and 2% O₂ during p-welldrive-in will reduce Q_(ss) to a level at which the n-channel devicewill operate at voltages greater than 15 volts without inversion betweenthe n^(+-source/drain) regions and the n-substrate. Preferably theQ_(ss) concentration is reduced to 1 × 10¹¹ /cm² or less in order to beable to operate the n-channel device at voltages up to 25 volts withoutthis inversion. It has also been found that Q_(ss) concentrations of 2 ×10¹¹ /cm² will reduce the operating limit of the n-channel device fromabout 25 volts to about 15 volts. It has been found that after p-welldrive-in, a treatment with water vapor will further reduce Q_(ss) byfilling in additional deficiency sites. While water vapor would work tofill in deficiency sites during p-well drive-in, there is an undesirableside effect of catalyzing additional oxide growth. In an ancillaryembodiment, water vapor is subsequently applied at a temperature in therange of 700°-1000° C. to further fill in deficiency sites.

The preferred Q_(ss) concentration recited above approaches the residualconcentration at the silicon/silicon dioxide interface produced by thesilicon-rich character of the silicon dioxide at the interface. Sincethe crystal orientation of the substrate determines the number ofsilicon atoms exposed per unit area on the surface of the planarsubstrate, the silicon-rich character of the silicon dioxide will dependupon underlying crystal structure. Thus, (100) silicon will have thelowest residual Q_(ss), on the order of 5 × 10¹⁰ /cm² and is therefore apreferred substrate material. While (110) and (111) orientation siliconhave, respectively, approximately twice and three times the residualQ_(ss) and can be used in the process of the present invention, thehigher residual Q_(ss) will affect the final Q_(ss) that can be achievedby curing the deficiency sites.

After the p-well drive-in, a layer of gate insulating material 30b and30d is formed in active device regions 15b and 15d. This gate materialis preferably silicon dioxide which is thermally grown to producedesirable interface characteristics with the underlying siliconsubstrate. This gate material may also be silicon nitride, Si₃ N₄, oralumina, Al₂ O₃. A layer of gate-forming conductive material 31 such asappropriately doped polycrystalline silicon is then chemically depositedover all regions of the device. As is well known in the semiconductorfabrication art, polycrystalline silicon can be used as a conductor ofholes if impregnated with a p-type impurity, or as a conductor ofelectrons if impregnated with an n-type impurity. The preferred dopantis phosphorus because the phosphorus forms a layer of glass at thesilicon gate/silicon dioxide interface which acts as an alkali barrierand getterer (neutralizer of alkaline radicals). The polycrystallinesilicon serves as gate electrodes and as a primary layer of electricalinterconnection of a double conductive layer device with aluminumserving as the upper or second layer.

Since gate insulating material 30 forms the electrical insulationbetween the conducting gate electrodes of the respective field-effectdevices and the semiconductor substrate, its physical characteristicsmust be closely controlled. For example, if region 30 is silicon dioxideand conductive material 31 is polycrystalline silicon, any sodium in thesilicon dioxide insulation constitutes a charge known as Q_(o) which mayimpair the performance of the device because it may drift through thesilicon dioxide, especially during high bias operation. If and when theQ_(o) charge drifts through the silicon dioxide, the threshold voltagescould be altered. For example, in the CMOS structure of the presentinvention, acceptable threshold voltage shifts are generally less thanone volt while Q_(o) drift can shift threshold voltages by several voltsor more. It has been found that doping the gate oxides with a chlorinespecies during formation retards such migration. It is not known whichparticular species is operative but the chlorine species are likely toinclude, among others, Cl, Cl₂, Cl⁻, Cl₂ ⁻, Cl₂ ⁻ ⁻. They may beintroduced by incorporation of a source of chlorine species such as HClor trichloroethylene in the oxidizing ambient. In one embodiment thefield oxide is similarly doped during thermal oxide growth to furtherenhance electrical stability by retarding impurity migration. Controland minimization of Q_(ss), the fixed surface state charge, in the gateoxide is also required to provide optimum threshold voltage control forthe active devices since it is known that Q_(ss) will shift thethreshold voltage in the negative direction. This control is achieved bypurging the oxidation ambient with an inert gas such as nitrogen orargon after the gate oxide is substantially formed and then cooling thegate oxide. See FIG. 5 of B. E. Deal et al., "Characteristics of theSurface-State Charge (Q_(ss)) of Thermally Oxidized Silicon," Journal ofElectrochemical Society, Vol. 114, No. 3 (1967).

Referring now to FIG. 4, conductive material 31 and insulating material30 is defined by a masking step to produce gate electrodes 34 and 35.The edges of the individual gates are configured to allow successivelayers to encounter a sloped contour. This sloped contour is achieved bya proprietary buffered etch process and serves to prevent cracking ofoverlying layers. Then, p-type impurities are predeposited into thesource/drain regions 36s and 36d (note that these regions are designatedsource/drain in the alternative because their character as source ordrain will depend on the way in which they are interconnected in aparticular circuit) of the p-channel device by a masking step whichselectively opens up these regions. Predeposition may be accomplished bydiffusion, ion implantation, sputtering or any related technique. Ifpredeposition is accomplished by diffusion, the as-yet-undefined gateoxide layer 30d prevents any p^(+-source/drain) impurities from enteringthe p-well. The gate electrode 34 serves as a definition mask so thatthe inner edges of regions 36s and 36d are self-aligned with the edgesof the gates. Alignment of the gates with the source/drain regionsprovides better performance by lowering junction capacitance and alsoproduces decreased device area. Any p-type impurities which reachpolycrystalline gates 34 and 35 only slightly affect the heavy n-typephosphorus doping. The n^(+-source/drain) diffusion regions for then-channel device are then formed by diffusion of an n-type conductivityimpurity such as phosphorus in a predeposition step. Silicon dioxide isused as a masking material rather than polymer photoresist because it isable to withstand diffusion furnace temperatures. Masking material 40 isthen removed by well-known etching techniques.

Referring now to FIG. 6, a layer 46 of additional electrical insulatingmaterial is formed across the surface of substrate 10 over isolationislands 20. In one embodiment this additional layer of material isformed by chemical deposition. The additional electrical insulationprovided by layer 46 inhibits conduction between n-region 37s andn-substrate 10 by increasing the voltage at which inversion of thesubstrate under oxide island 20 will occur. The drive-in of both p-typeand n-type source/drain diffusion regions is then accomplished byheating the substrate to a temperature of about 1070° C. for aboutone-half hour. The p-well and field implant are only slightly affectedbecause they previously had been driven in by a drive-in at about 1200°C. for about 16 hours.

The complementary field-effect transistor structure is then completed asshown in FIG. 7 by applying conductive connectors and defining them toproduce metal layer 50 which interconnects p-region 36d and n-region 37sand metal layers 51 and 52 which provide electrical contact withp-region 36s and n-region 37d, respectively. Interconnection of onesource/drain region of the p-channel device and one source/drain regionof the n-channel device produces a complementary field-effect circuitwith the switching properties described above. In an alternateembodiment, the source/drain regions of complementary devices are notinternally connected, in order to allow circuit designers to arrangesource/drain interconnections externally. An anneal of the structure ina hydrogen-containing ambient in the temperature range of 350°-500° C.is carried out to minimize the fast interface state density, which alsoadversely affects threshold voltages and other device characteristics.Finally, scratch-protection layers and packaging is provided inaccordance with established practices.

The above-described fabrication process produces an improvedoxide-isolated silicon gate complementary field-effect structure. Asshown in FIGS. 1-7, an MOS device with a p-channel conductivity type(channel is p-type when device conducts) is formed in active deviceregion 15b and an MOS device with an n-channel conductivity type(channel is n-type when device conducts) is formed in active deviceregion 15d. In one embodiment the source/drain regions are 1.2μ deep,the p-well is 10μ deep, the gate oxide is 0.1μ thick and the gateelectrodes 0.4μ thick. Each device is surrounded by isoplanar oxideisolation which is about 1.5μ deep. (From these values it is evidentthat the FIGURES are pictorial and not drawn to scale.) Whileoxide-isolated CMOS structures with individual p-wells have beenproposed (See R. N. Finella et al., "CMOS III: A High Density IonImplanted CMOS Technology," Proceedings of the Technical Program, 1971Semiconductor/IC Processing & Production Conference, pp. 7-10), theparticular structure of the present invention has not previously beendescribed or realized. The present invention, for the first time,discloses counterdoping of p-type with n-type impurities in the p-wellto produce a high concentration deep within the well to preventinversion between the n^(+-source/drain) regions and the n-substrate,and to produce a low concentration near the surface of the substrate toprovide a low threshold voltage for the n-channel device. The mixture ofthe two impurity types produces a doping profile that has not previouslybeen achieved. Also, the fixed charge Q_(ss) in the silicon dioxide nearthe silicon/silicon dioxide interface is at a reduced level, preferablybelow 1 × 10¹¹ /cm², so that inversion between the n^(+-source/drain)region and the n-substrate is further inhibited. In one embodiment, anoperating voltage range of from 3 to more than 15 volts is achieved. Thecombination of isoplanar oxide isolation and polycrystalline silicongates results in high density, lower capacitance and a more planartopography. In particular, the doping of the polycrystalline siliconwith phosphorus produces a thin layer of glass at the silicongate/silicon dioxide interface which acts as an alkali getterer andbarrier. The polycrystalline silicon gate electrodes are self-alignedwith the source/drain regions to produce devices with reduced junctioncapacitance. The presence of an n-type field implant in the p-welladjacent the oxide isolation islands inhibits inversion of the p-wellunderneath the isolation islands. Finally, the presence of a chlorinespecies in the gate and field oxides reduces the likelihood that mobileimpurity ions can produce inversion of the substrate or the p-well.

What is claimed is:
 1. A process for fabricating a complementaryinsulated gate field effect transistor structure wherein p-channel andn-channel devices are formed within the same semiconductor substrate,comprising:a. applying a thermal oxidation masking material to a layerof n-type silicon including depositing a layer of silicon dioxide anddepositing a layer of silicon nitride on said layer of silicon oxide; b.defining said thermal oxidation material to establish protected activedevice regions and to open up isoplanar isolation regions; c introducinga lightly doped n-type impurity in the substrate in isoplanar isolationregions; d. heating said semiconductor substrate in the presence of anoxidizing agent to form isolation islands of silicon dioxide; e.removing said thermal oxidation masking material; f. predepositingn-type and p-type impurities in at least one active device region; g.heating said substrate in an atmosphere containing less than 5 percentof an oxidizing agent to drive said n-type and p-type impurities intosaid substrate to form a composite conductivity well, the relativeconcentration of said n-type and p-type impurities producing a low netp-type concentration near the surface of said well and high net p-typeconcentration deep within said well; h. thermally growing a thin layerof silicon dioxide in said active device regions; i. depositing aconductive layer of polycrystalline silicon; j. defining said layers ofsilicon dioxide and polycrystalline silicon to produce insulated gateelectrodes for the p-channel and n-channel devices; k. predepositingboron adjacent both sides of a defined gate electrode in an activedevice region formed in said layer of n-type silicon to form thesource/drain regions of a p-channel field effect device; l.predepositing phosphorus adjacent both sides of a defined gate electrodein an active device region formed in said composite well to produce thesource/drain regions of an n-channel field effect device; m. thermallydriving in said impurities predeposited in said source/drain regions ofsaid p-channel and n-channel devices; n. forming a further layer ofelectrical insulation over said isolation islands; and o. applying aconductive layer and defining said conductive layer to connect one ofsaid source-drain regions of said p-channel field effect device and oneof said source/drain regions of said n-channel field effect device andto effect external electrical coupling with the remaining source/drainregions of said n-channel and p-channel field effect devices.
 2. Aprocess for fabricating a complementary insulated gate field effecttransistor structure in accordance with claim 1 wherein the steps of (d)and (h) further comprise heating in the presence of a gas containing achlorine species.
 3. A process for fabricating a complementary insulatedgate field effect transistor structure in accordance with claim 2wherein step (i) further comprises doping said layer of polycrystallinesilicon with phosphorus.